This application claims the benefit of Korean Patent Application No. 2001-48288, filed Aug. 10, 2001, the disclosure of which is hereby incorporated herein by reference.
The present invention relates generally to integrated circuit devices and methods of forming same and, more particularly, to integrated circuit memory devices and methods of forming same.
As the integration density of integrated circuit devices increases, the size of transistors used therein may be reduced. In addition, the length of gates and/or the thickness of gate oxide layers may be reduced. By reducing the thickness of a gate oxide layer, the operational speed of an integrated circuit device may be increased; however, the reduced gate oxide layer thickness may increase the susceptibility to break down.
Integrated circuit devices may include memory cell areas that occupy relatively large amounts of chip area. If a gate oxide layer has a uniform thickness throughout a chip, then break down is generally more likely to occur first in a memory cell area, which may degrade operation. To address this problem, a gate oxide layer may be more thickly formed in a cell array area than in a logic circuit area because break down voltage typically increases as the gate oxide layer thickness is increased and decreases as the gate oxide layer thickness is decreased. Thus, to enhance reliability of an integrated circuit device, the thickness of gate oxide layers in the cell array area may be different than the thickness of the gate oxide layers in the logic circuit area.
Integrated circuit devices may comprise a highly integrated DRAM and one or more high-speed logic circuits in the same chip. The gate patterns in the cell array area may be self-aligned and may have stacked gate structures, which are protected by a silicon nitride layer (SiN). These patterns may be called stacked gate patterns. Gate patterns in the logic circuit area may comprise silicide gate structures having a surface channel. These patterns may be called silicide gate patterns. A device that comprises both a stacked gate pattern and a suicide gate pattern may be called a merged device.
When forming stacked gate patterns and/or silicide gate patterns, the threshold voltage of a merged device may change and/or boron from a PMOS transistor may break away due to heat generated during a thermal treatment that is applied during the fabrication process.
According to some embodiments of the present invention, an integrated circuit device, such as a merged device, is formed by forming a first gate oxide layer on a first region, such as a logic circuit region, of a substrate. A conductive layer is formed on the first gate oxide layer. A second gate oxide layer is formed on a second region, such as a cell array region, of the substrate. A first gate pattern is formed on the second gate oxide layer. The conductive layer and the first gate oxide layer are patterned to form a second gate pattern. A silicide layer is formed on the second gate pattern and in the substrate adjacent to the second gate pattern.
In other embodiments of the present invention, the second gate oxide layer is formed on the conductive layer and on the cell array region of the substrate. Patterning the conductive layer and the first gate oxide layer may include the operations of forming an anti-reflective layer on the second gate oxide layer in the logic circuit region of the substrate, patterning the anti-reflective layer to form an anti-reflective layer pattern, and etching the second gate oxide layer, the conductive layer, and the first gate oxide layer using the anti-reflective layer pattern as an etching mask to form the second gate pattern. The anti-reflective layer may comprise at least one of SiN and SiON.
In still other embodiments, the conductive layer is a first conductive layer and operations for forming the first gate pattern include forming a second conductive layer on the second gate oxide layer, forming a polycide layer on the second conductive layer, forming a silicon nitride layer on the second conductive layer, forming a mask pattern on the silicon nitride layer, and etching the silicon nitride layer, the polycide layer, and the second conductive layer using the mask pattern as an etching mask. In particular embodiments, the first conductive layer is at least as thick as the second conductive layer.
Although embodiments of the present invention have been described above primarily with respect to fabrication method embodiments, embodiments of integrated circuit devices formed by such fabrication methods are also provided.